IC 驗證工程師 (Design Verification Engineer) (新竹) - TrustTeks Ltd.|Meet.jobs

薪資

1.3m+ TWD Annually

技能需求
  • C++
  • ,
  • Perl
  • ,
  • Python
  • ,
  • TCL
  • ,
  • ASIC
  • ,
  • Verilog
  • ,
  • UVM
  • ,
  • Systemverilog

工作機會描述

Use System Verilog and UVM verification methodology to verify ASIC designs for data storage systems.
使用System Verilog和UVM的驗證方法來驗證針對資料儲存系統所設計的數位電路。

You will
Responsible for verification of the digital design, golden models using methodologies such as UVM
Understand the design and operation sequence, develop verification structure and verify the correctness of the design.
Dive into the bottom of Verification skill/Storage technique/Root of the problem

Qualifications
1. Willing to learn
2. Highly proactive and open-minded
3. Smart guys
我們是一群喜歡學習,主動積極,聰明的人,想找尋擁有一樣特性的人一起加入新創公司。

Preferred requirement
1. Master degree in EE or CS
2. Familiar with System Verilog and UVM
3. Familiar with storage system

TrustTeks Ltd.

我們擁有頂尖的技術,重視每個IP的品質,讓員工能發揮所長學以致用,並注重員工家庭與工作的平衡。

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