PCIe Design Engineer/Leader - TrustTeks Ltd.｜Meet.jobs
薪資
2m - 3m TWD Annually
技能需求
- Systemverilog,
- verilog,
- fpga,
- management
工作機會描述
Responsible for PCIe Controller design, integration and simulation.
Debug PCIe-related issue in ASIC or FPGA.
Work with HW and FW team closely for the product development.
Lead a design team.
Requirement:
Master's degree in electrical or electronics engineering.
At least 10 years (preferred) experiences in RTL design and verification.
Design experience in High Speed IO Controllers like PCIe or SATA.
Good ability to integrate Phy IP.
Familiar with FPGA and silicon debug.
Good communication skill and team working spirit.
TrustTeks Ltd.
我們擁有頂尖的技術，重視每個IP的品質，讓員工能發揮所長學以致用，並注重員工家庭與工作的平衡。