資深 IC 驗證工程師 (Senior Design Verification Engineer) (新竹) - TrustTeks Ltd.｜Meet.jobs
薪資
1.8m+ TWD Annually
技能需求
- RTL,
- Systemverilog,
- verilog,
- C,
- UVM
工作機會描述
Use System Verilog and UVM verification methodology to verify ASIC designs for data storage systems.
You will
Responsible for verification of the digital design, golden models using methodologies such as UVM
Understand the design and operation sequence, develop verification structure, compose fw sequence and verify the correctness of the design.
Review test bench architecture, flow and tb integration.
Communicate between Design Engineer and Firmware Engineer to come out efficient testplan and bug hunting.
Qualifications
1. Strong experience in digital design verification
2. Willing to learn
3. Highly proactive and open-minded
4. Smart guys
Preferred requirement
1. Master degree in EE or CS
2. Familiar with System Verilog and UVM
3. Above 5 years experience in verification.
4. Familiar with storage system.
TrustTeks Ltd.
我們擁有頂尖的技術，重視每個IP的品質，讓員工能發揮所長學以致用，並注重員工家庭與工作的平衡。