IC Layout Engineer, 晶片佈局工程師 - Tensorcom｜Meet.jobs

Tensorcom, a pioneer in developing innovative semiconductors for high-speed millimeter wave, ultra-low power,  wireless communication chipsets, is looking for a candidate who is interested in analog circuit layout for our next generation 60GHz, IEEE 802.11ad/ay compliant SoCs.

 

In addition to excellent technical skills, good English communication skills are required.

Responsibilities

The interested candidate will be responsible for:

·        Setting up the LVS, DRC, ERC environments and debugging verification issues using the Cadence tool suite

·        Collaborating with an interdisciplinary functional team to define and develop the design flow, optimization of the silicon floor plan, and bump and package pinouts.

·        Setting up design rules and implementing in-house packaging layout to meet product requirements.

·        Optimizing package design to maintain signal and power integrity

·         Paying attention to lay out details and providing documentation

Qualifications:

The interested candidate shall have demonstrable experience and/or knowledge in:

·        The proficient use of the IC5 & 6.x Cadence Virtuoso tool suite

·        Layout techniques for device matching, parasitic minimization, RF shielding, and high frequency routing

·        The fundamentals of RC delay, EMI, and Crosstalk

·        IC packaging structures, chip-packaging, and package-board interactions.

·        The details of the semiconductor process and device physics

·        Laying out high speed I/O interfaces such as PCIe3.x, USB3.x, and GigE.

EDUCATION / MAJOR
■ BS /  ■ MS

Electrical or Computer Engineering, Communications Engineering, or similar applicable technical degrees.

 

EXPERIENCE
5+ / 3+ years